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integrated silicon solution, inc. 1 rev. a 06/01/09 copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. is43r16800cc 8mx16 128mb ddr synchronous dram address table parameter 8m x 16 confguration 2m x 16 x 4 banks bank address pins ba0, ba1 autoprecharge pins a10/ap row addresses a0 C a11 column addresses a0 C a8 refresh count 4096 / 64ms key timing parameters parameter -5 -6 -75 unit clk cycle time cas latency = 3 5 6 7.5 ns cas latency = 2.5 5 6 7.5 ns cas latency = 2 7.5 7.5 7.5 ns clk frequency cas latency = 3 200 167 133 mhz cas latency = 2.5 200 167 133 mhz cas latency = 2 133 133 133 mhz access time from clock cas latency = 3 +0.70 +0.70 +0.75 ns cas latency = 2.5 +0.70 +0.70 +0.75 ns cas latency = 2 +0.75 +0.75 +0.75 ns june 2009 features: v ? d d =v d d q = 2.5v+0.2v (-5, -6, -75) double data rate architecture; two data transfers ? per clock cycle. bidirectional , data strobe (dqs) is transmitted/ ? received with data differential clock input (clk and /clk) ? dll aligns dq and dqs transitions with clk ? transitions edges of dqs commands entered on each positive clk edge; ? data and data mask referenced to both edges of ? dqs 4 bank operation controlled by ba0 , ba1 ? (bank address) /cas latency -2.0 / 2.5 / 3.0 (programmable) ; ? burst length -2 / 4 / 8 (programmable) burst type -sequential / interleave (program- mable) auto precharge/ all bank precharge controlled ? by a10 4096 refresh cycles / 64ms (4 banks concurrent ? refresh) auto refresh and self refresh ? row address a0-11 / column address a0-8 ? sstl_2 interface ? package: ? 66-pin tsop ii temperature range: ? commercial (0 o c to +70 o c) industrial (-40 o c to +85 o c) description: is43r16800cc is a 4-bank x 2,097,152-word x 16bit double data rate synchronous dram , with sstl_2 interface. all control and address signals are referenced to the rising edge of clk. input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of clk. the device achieves very high speed clock rate up to 200 mhz.
2 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc pin configurations 66 pin tsop - type ii for x16 v dd dq0 v dd q dq1 dq2 v ss q dq3 dq4 v dd q dq5 dq6 v ss q dq7 nc v ddq ldqs nc vdd nc ldm we cas ras cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq9 v dd q dq8 nc v ssq udqs nc vref vss udm ck ck cke nc nc a11 a9 a8 a7 a6 a5 a4 vss pin description: a0-a11 row address input a0-a8 column address input ba0, ba1 bank select address dq0 C dq15 data i/o clk, clk system clock input cke clock enable cs chip select cas column address strobe command ras row address strobe command we write enable ldm, udm data write mask ldqs, udqs data strobe vdd power vddq power supply for i/o pins vss ground vssq ground for i/o pins vref sstl_2 reference voltage nc no connection
integrated silicon solution, inc. 3 rev. a 06/01/09 is43r16800cc i i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary pin function clk, /clk input clock: clk and /clk are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of clk and negative edge of /clk. output (read) data is referenced to the crossings of clk and /clk (both directions of crossing). cke input clock enable: cke controls internal clock. when cke is low, internal clock for the following cycle is ceased. cke is also used to select auto / self refresh. after self refresh mode is started, cke becomes asynchronous input. self refresh is maintained as long as cke is low. /cs input chip select: when /cs is high, any command means no operation. /ras, /cas, /we input combination of /ras, /cas, /we defines basic commands. a0-1 1 input a0-1 1 specify the row / column address in conjunction with ba0,1. the row address is specified by a0-1 1 . the column address is specified by a0-8. a10 is also used to indicate precharge option. when a10 is high at a read / write, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. ba0,1 input d dq0-15 input / output d v dd , v ddq, v ddq, and v ss power supply power supply for the memory array and peripheral circuitry. v ssq power supply v ssq are supplied to the output buffers only. bank address: ba0,1 specifies one of four banks to which a command is applied. ba0,1 must be set with act, pre, read, write commands. data input/output: data bus data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. used to capture write data. for the x16, ldqs corresponds to the data on dq0-dq7; udqs correspond to the data on dq8-dq15 symbol type description d input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. for the x16, ldm corresponds to the data on dq0-dq7; udm corresponds to the data on dq8-dq15. input / output vref input sstl_2 reference voltage. udqs, ldqs udm, ldm
4 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc block diagram x16 /c s/ ras /c as /we udm , ld m me mo ry arra y ba nk #0 dq 0- 15 i/ ob uf fe r me mo ry arra y ba nk #1 me mo ry arra y ba nk #2 me mo ry arra y ba nk #3 mo de re gist er co nt ro lc ircu itry addres sb uf fer a0-11 ba 0, 1 cl oc kb uf fer clk cke co nt ro ls ig na lb uf fer dq sb uf fe r udqs, ld qs dl l /c lk
integrated silicon solution, inc. 5 rev. a 06/01/09 is43r16800cc i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary basic functions issi's 128-mbit ddr sdram provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. each command is defined by control signals of /ras, /cas and /we at clk rising edge. in addition to 3 signals, /cs , cke and a10 are used as chip select, refresh option, and precharge option, respectively. to know the detailed definition of commands, please see the command truth table. /cs chip select : l=select, h=deselect /ras command /cas command /we command cke refresh option @refresh command a10 precharge option @precharge or read/write command clk define basic commands /clk activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, the bank is deactivated after the burst read (auto- precharge, reada ) write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write (auto-precharge, writea ) precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this command also terminates burst read /write operation. when a10 =h at this command, all banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke =h] refa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically.
6 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc i i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary command truth table h=high level, l=low level, v=valid, x=don't care, n=clk cycle number note: 1. applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for read bursts with autoprecharge enabled, and for write bursts. 2. ba0-ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register;ba0=1 , ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserved; a0-a1 1 provide the op-code to be written to the selected mode register. command mnemonic cke n-1 cke n /cs /ras /cas /we ba0,1 a10 /ap a0-9, 11 deselect desel h x h x x x x x x no operation nop h x l h h h x x x row address entry & bank activate act h h l l h h v v v single bank precharge pre h h l l h l v l x precharge all banks prea h h l l h l h x column address entry & write write h h l h l l v l v column address entry & write with auto-precharge writea h h l h l l v h v column address entry & read read h h l h l h v l v column address entry & read with auto-precharge reada h h l h l h v h v auto-refresh refa h h l l l h x x x self-refresh entry refs h l l l l h x x x self-refresh exit refsx l h h x x x x x x l h l h h h x x x burst terminate term h h l h h l x x x mode register set mrs h h l l l l l l v x note 1 2
integrated silicon solution, inc. 7 rev. a 06/01/09 is43r16800cc zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary function truth table current state /cs /ras /cas /we address command action notes idle h x x x x desel nop l h h h x nop nop l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop 4 l l l h x refa auto-refresh 5 l l l l op-code, mode- add mrs mode register set 5 row active h x x x x desel nop l h h h x nop nop l h h l ba term illegal l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge / precharge all l l l h x refa illegal l l l l op-code, mode- add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin new read, determine auto- precharge 3 l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode- add mrs illegal read(auto- precharge disabled)
8 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc i i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary function truth table (continued) current state /cs /ras /cas /we address command action notes h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin read, determine auto-precharge 3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto-precharge 3 l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode- add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge / illegal 2 l l l h x refa illegal l l l l op-code, mode- add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge / illegal 2 l l l h x refa illegal l l l l op-code, mode- add mrs illegal write(auto- precharge disabled) read with auto-precharge write with auto-precharge
integrated silicon solution, inc. 9 rev. a 06/01/09 is43r16800cc zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary function truth table (continued) current state /cs /ras /cas /we address command action notes h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre / prea nop (idle after trp) 4 l l l h x refa illegal l l l l op-code, mode- add mrs illegal h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre / prea illegal 2 l l l h x refa illegal l l l l op-code, mode- add mrs illegal h x x x x desel nop l h h h x nop nop l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre / prea illegal 2 l l l h x refa illegal l l l l op-code, mode- add mrs illegal row activating write re- covering pre- charging
10 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc i i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary function truth table (continued) abbreviations: h=high level, l=low level, x=don't care ba=bank address, ra=row address, ca=column address, nop=no operation notes: 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba. 5. illegal if any bank is not idle. illegal = device operation and/or data-integrity are not guaranteed. current state /cs /ras /cas /we address command action notes refreshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode- add mrs illegal h x x x x desel nop (row active after trsc) l h h h x nop nop (row active after trsc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode- add mrs illegal mode register setting
integrated silicon solution, inc. 11 rev. a 06/01/09 is43r16800cc zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary function truth table for cke abbreviations: h=high level, l=low level, x=don't care notes: 1. cke low to high transition will re-enable clk and other inputs asynchronously. a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only from the all banks idle state. 3. must be legal command. current state cke n-1 cke n /cs /ras /cas /we address action notes h x x x x x x invalid 1 l h h x x x x exit self-refresh (idle after trc) 1 l h l h h h x exit self-refresh (idle after trc) 1 l h l h h l x illegal 1 l h l h l x x illegal 1 l h l l x x x illegal 1 l l x x x x x nop (maintain self-refresh) 1 h x x x x x x invalid l h x x x x x exit power down to idle l l x x x x x nop (maintain self-refresh) h h x x x x x refer to function truth table 2 h l l l l h x enter self-refresh 2 h l h x x x x enter power down 2 h l l h h h x enter power down 2 h l l h h l x illegal 2 h l l h l x x illegal 2 h l l l x x x illegal 2 l x x x x x x refer to current state =power down 2 h h x x x x x refer to function truth table h l x x x x x begin clk suspend at next cycle 3 l h x x x x x exit clk suspend at next cycle 3 l l x x x x x maintain clk suspend any state other than listed above self- refreshing power down all banks idle
12 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc i i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary simplified state diagram row active idle pre charge power down read reada write writea power on act refa refs refsx ckel ckeh mrs ckel ckeh write read writea writea reada read pre reada reada pre pre prea power applied mode register set self refresh auto refresh active power down automatic sequence command sequence write read pre charge all mrs burst stop term
integrated silicon solution, inc. 13 rev. a 06/01/09 is43r16800cc power on seque nce before starting normal operation, the following power on sequence is n ece ss ary to prevent a sdram from damaged or multifunctioning. 1. apply vdd before or the same t im e as vddq 2. apply vddq before or at the same t im e as vt t & vref 3. maintain stable condition for 200us after stable power and clk , apply no p or dsel 4. i ss ue pr ec harge co mm and for a ll banks of the device 5. i ssue e mrs 6. i ss ue mrs for the mode register and to reset the dll 7. i ss ue 2 or more auto refresh commands 8. maintain stable condition for 200 cycle after these sequence , the dd r sdram is idle state and r ea dy for normal operation. mode regis ter burst length, burst type and /cas latency ca n be programmed by setting the mode register (mrs). the mode register stores these data unt il the next mrs command, which may be i ss ued when all banks are in idle state. after tmrd from a mrs command , the dd r sdram is r ea dy for new co mm and. /cs /ras /cas /we a11-a0 /clk v clk ba0 ba1 r: reserved for future use 0 no 1 yes dll reset 0 se qu ential 1 interl ea ved burst type bt=0 bt=1 0 0 0 r r 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 r r 1 0 1 r r 1 1 0 r r 1 1 1 r r bl burst length /cas latency 0 0 0 r 0 0 1 r 0 1 0 2 0 1 1 3 1 0 0 r 1 0 1 r 1 1 0 2.5 1 1 1 r cl latency m ode ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 dr 0 bt ltmode bl
14 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc ex tend ed mode regis ter d ll disable / enable mode ca n be progra mm ed by setting the extended mode register (emrs). the extended mode register stores these data unt il the next emrs co mm and, which may be i ss ued when all banks are in idle state. after tmrd from a emrs co mm and, the dd r sdram is r ea dy for new command. /cs /ras /cas /we a11-a0 v ba0 ba1 /clk clk ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 10 0 0 0 0 0 0 0 0 0 ds dd 0 normal 1 w eak drive strength 0 dll enable 1 d ll disable d ll disable
integrated silicon solution, inc. 15 rev. a 06/01/09 is43r16800cc zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary /cas latency burst length cl= 2 bl= 4 burst length a2 a1 a0 initial address bl sequential interleaved column addressing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 8 4 2 command address dq y y read write dqs q0 q1 q2 q3 d0 d1 d2 d3 /clk clk
16 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc absolute maximum ratings dc operating conditions (ta=0 ~ 70 o c, unless otherwise noted) capacitance (ta=0 ~ 70 o c, vdd = vddq = 2.5v + 0.2v vss = vssq = 0v, unless otherwise noted) min. max. ci(a) input capacitance, address pin vi=1.25v 1.3 2.5 pf ci(c) input capacitance, control pin f=100mhz 1.3 2.5 pf ci(k) input capacitance, clk pin vi=25mvrms 1.3 2.5 0.25 pf ci/o i/o capacitance, i/o, dqs, dm pin 2 4 1.3 pf 0.75 notes limits symbol parameter test condition unit delta cap.(max.) min. typ. max. supply voltage 2.3 2.5 2.7 v -5, -6, -75 -5, -6, -75 supply voltage for output 2.3 2.5 2.7 v high-level input voltage vref+0.15 vdd+0.3 v low-level input voltage -0.3 vref-0.15 v input leakage current any input 0v integrated silicon solution, inc. 17 rev. a 06/01/09 is43r16800cc -5 -6 -75 idd1 operating current: one bank; active-read-precharge;burst = 2; t rc = t rc min; t ck = t ck min; iout= 0ma; address and control inputs changing once per clock cycle 185 165 150 idd5 auto refresh current: t rc = t rfc (min) 170 160 150 idd6 self refresh current: cke < 0.2v 5 5 5 active standby current: /cs > vih (min); cke > vih (min); one bank; active-precharge; t rc = t ras max; t ck = t ck min; dq,dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle idd3n idd2p idd2n idle standby current: /cs > vih (min); all banks idle; cke > vih (min); t ck = t ck min; address and other control inputs 60 changing once per clock cycle idd3p active power down standby current: one bank active;power down mode;cke vil(max);t ck = t ck min 250 210 limits(max.) 25 20 75 55 30 50 210 notes symbol parameter/test conditions ma unit idd4w operating current: burst =2; write ; continuous burst;all banks active; address and control inputs changing once per clock cycle;t ck = t ck min; dq and dqs inputs changing twice per clock cycle precharge power-down standby current: all banks idle; power-down mode; cke < vil (max); t ck = t ck min 290 50 95 idd4r operating current: burst =2; read ; continuous burst;all banks active; address and control inputs changing once per clock cycle;t ck = t ck min; iout = 0 ma 290 250 90 45 40 average supply current from vdd ( o c ( vdd = vddq = 2.5v + 0.2v, vss = vssq = 0v, output open, unless otherwise noted)
18 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc i i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary ac timing requirements min. max min. max min. max tac dq output access time from clk//clk -0.70 +0.70 -0.70 +0.70 -0.75 +0.75 ns tdqsck dqs output access time from clk//clk -0.6 +0.6 -0.60 +0.60 -0.75 +0.75 ns tch clk high level width 0.45 0.55 0.45 0.55 0.45 0.55 tck tcl clk low level width 0.45 0.55 0.45 0.55 0.45 0.55 tck cl=3.0 5 7.5 6 12 7.5 12 ns cl=2.5 5 12 6 12 7.5 12 ns cl=2.0 7.5 12 7.5 12 7.5 12 ns tds input setup time (dq,dm) 0.4 0.45 0.5 ns tdh input hold time(dq,dm) 0.4 0.45 0.5 ns tipw control & address input pulse width (for each input) 2.2 2.2 2.2 ns tdipw dq and dm input pulse width (for each input) 1.75 1.75 1.75 ns thz data-out-high impedance time from clk//clk +0.70 +0.70 +0.75 ns 14 tlz data-out-low impedance time from clk//clk -0.70 +0.70 -0.70 +0.70 -0.75 +0.75 ns 14 tdqsq dq valid data delay time from dqs 0.40 0.45 0.5 ns thp clock half period tclmin or tchmin tclmin or tchmin tclmin or tchmin ns 20 tqh dq output hold time from dqs (per access) thp-tqhs thp-tqhs thp-tqhs ns tqhs data hold skew factor (for dqs & associated dq signals) 0.50 0.55 0.75 tdqss write command to first dqs latching transition 0.72 1.25 0.75 1.25 0.75 1.25 tck tdqsh dqs input high level width 0.35 0.35 0.35 tck tdqsl dqs input low level width 0.35 0.35 0.35 tck tdss dqs falling edge to clk setup time 0.2 0.2 0.2 tck tdsh dqs falling edge hold time from clk 0.2 0.2 0.2 tck tmrd mode register set command cycle time 2 2 2 tck twpres write preamble setup time 0 0 0 ns 16 twpst write postamble 0.4 0.6 0.4 0.6 0.4 0.6 tck 15 twpre write preamble 0.25 0.25 0.25 tck tis input setup time (address and control) 0.6 0.75 0.9 ns 19 tih input hold time (address and control) 0.6 0.75 0.9 ns 19 trpst read postamble 0.4 0.6 0.4 0.6 0.4 0.6 tck trpre read preamble 0.9 1.1 0.9 1.1 0.9 1.1 tck tck symbol ac characteristics parameter -5 notes -6 clk cycle time -75 unit
integrated silicon solution, inc. 19 rev. a 06/01/09 is43r16800cc ac timing requirement s( continues) min. max min. max min. max tras row active time 40 120,000 42 120,000 45 120,000 ns trc row cycle t im e(operation) 55 60 65 ns trfc auto ref. to active/auto ref. command period 70 72 75 ns trcd row to column delay 15 18 20 ns trp row pr ec harge time 15 18 20 ns t rr d act to act delay time 10 12 15 ns twr write r ec overy t ime 15 15 15 ns t da l auto pr ec harge write r ec overy + pr ec harge t im e twr+trp twr+trp twr+trp ns twtr internal write to r ea d comm and delay 2 1 1 tck txsnr exit self ref. to non-r ea d comm and 75 75 75 ns txsrd exit self ref. to -r ea d command 200 200 200 tck txpnr exit power do wn to command 1 1 1 tck s txprd exit power do wn to -r ea d comm and 1 1 1 tck 18 trefi average periodic refresh interval 15.6 15.6 15.6 17 -75 unit notes symbol ac char ac teristics parameter -5 -6 output load condition dq output timi ng measurement referen ce point v ref v ref dqs v out v ref 30pf 50 ? v tt =v ref zo=50 ?
20 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc i i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary notes 1. all voltages referenced to vss. 2. tests for ac timing, idd, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. ac timing and idd tests may use a vil to vih swing of up to 1.5v in the test environment, but input timing is still referenced to vref (or to the crossing point for ck//ck), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between vil(ac) and vih(ac). 4. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 5. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on vref may not exceed + 2% of the dc value. 6. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set equal to vref, and must track variations in the dc level of vref. 7. vid is the magnitude of the difference between the input level on clk and the input level on /clk. 8. the value of vix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. 9. enables on-chip refresh and address counters. 10. idd specifications are tested after the device is properly initialized. 11. this parameter is sampled. vddq = 2.5v+ 0.2v, vdd = 2.5v + 0.2v , f = 100 mhz, ta = 25 o c, vout(dc) = vddq/2, vout(peak to peak) = 25mv. dm inputs are grouped with i/o pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). 12. the clk//clk input reference level (for timing referenced to clk//clk) is the point at which clk and /clk cross; the input reference level for signals other than clk//clk, is vref. 13. inputs are not recognized as valid until vref stabilizes. exception: during the period before vref stabilizes, cke< 0.3vddq is recognized as low. 14. t hz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz), or begins driving (lz). 15. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this clk edge. a valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from high-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 17. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 18. txprd should be 200 tclk in the condition of the unstable clk operation during the power down mode. 19. for command/address and ck & /ck slew rate > 1.0v/ns. 20. min (tcl,tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device. timing patterns: tck=min,trrd=2*tck,bl=4,trcd=3*tck,read with autoprecharge read:a0 n a1 r0 a2 r1 n r3 a0 n a1 r0 C repeat the same timing with random address changing *100% of data changing at every burst legend: a=activate,r=read,p=precharge,n=nop
integrated silicon solution, inc. 21 rev. a 06/01/09 is43r16800cc /clk dqs tis tih vref clk valid data read operation tac tdqsck tcl tch tck tdqsq tqh trpre trpst dqs /clk clk tdqss tds tdh tdqsl tdqsh twpre write operation / tdqss=max. tdss twpres twpst dqs /clk clk tdqss tds tdh tdqsl tdqsh twpre write operation / tdqss=min. tdsh twpres twpst dq dq dq cmd & add.
22 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc i i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary the ddr sdram has four independent banks. each bank is activated by the act command with the bank addresses (ba0,1). a row is indicated by the row address a0-1 1 . the minimum activation interval between one bank and the other bank is trrd. bank activate operational description the pre command deactivates the bank indicated by ba0,1. when multiple banks are active, the precharge all command (prea,pre+a10=h) is available to deactivate them at the same time. after trp from the precharge, an act command to the same bank can be issued. precharge bank activation and precharge all (bl=8, cl=2) a precharge command can be issued at bl/2 from a read command without data loss. precharge all command a0-9,11 a10 ba0,1 dq act xa xa 00 read y 0 00 act xb xb 01 pre trrd trcd 1 act xb xb 01 tras trp trcmin 2 act command / trcmin dqs qa0 bl/2 qa1 qa2 qa3 qa4 qa5 qa6 qa7 /clk clk
integrated silicon solution, inc. 23 rev. a 06/01/09 is43r16800cc i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary after trcd from the bank activation, a read command can be issued. 1st output data is available after the /cas latency from the read, followed by (bl-1) consecutive data when the burst length is bl. the start address is specified by a0-8, and the address sequence of burst data is defined by the burst type. a read command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data by interleaving the multiple banks. when a10 is high at a read command, the auto-precharge (reada) is performed. any command(read,write,pre,act) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at bl/2 after reada. the next act command can be issued after (bl/2+trp) from the previous reada. read multi bank interleaving read (bl=8, cl=2) /clk command a0-9,11 a10 ba0,1 dq act xa xa 00 read y 0 00 read y 0 10 act xb xb 10 pre 0 00 trcd /cas latency burst length dqs qa0 clk qa1 qa2 qa3 qa4 qa5 qa6 qa7 qb0 qb1 qb2 qb3 qb4 qb5 qb7 qb8
24 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc trcd trp bl/2 bl/2 + trp read with auto-precharge (bl=8, cl=2,2.5,3.0) command a0-9,11 a10 ba0,1 dq act xa xa 00 read y 1 00 dqs /clk clk internal precharge start timing qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 dq dqs qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 cl=2 cl=2.5 0 1 2 3 4 5 6 7 8 9 10 11 12 dq dqs qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 cl=3.0
integrated silicon solution, inc. 25 rev. a 06/01/09 is43r16800cc i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary after trcd from the bank activation, a write command can be issued. 1st input data is set from the write command with data strobe input, following (bl-1) data are written into ram, when the burst length is bl. the start address is specified by a0-8, and the address sequence of burst data is defined by the burst type. a write command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous input data by interleaving the multiple banks. from the last data to the pre command, the write recovery time (twrp) is required. when a10 is high at a write command, the auto-precharge(writea) is performed. any command(read,write,pre,act) to the same bank is inhibited till the internal precharge is complete. the next act command can be issued after tdal from the last input data cycle. write multi bank interleaving write (bl=8) command a0-9,11 a10 ba0,1 dq act xa 00 write 00 write 0 0 10 act xb 10 0 10 trcd d trcd d pre xa 0 00 pre dqs /clk clk da0 da1 da2 da3 da4 da5 da6 da7 db0 db1 db2 db3 db4 db5 db6 db7 xa ya yb xb
26 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc i i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary write with auto-precharge (bl=8) command a0-9,11 a10 ba0,1 dq act xa 00 write 1 00 act xb 00 trc d da0 dqs /clk clk da1 da2 da3 da4 da5 da6 da7 tdal xa y xb 0 1 2 3 4 5 6 7 8 9 10 11 12
integrated silicon solution, inc. 27 rev. a 06/01/09 is43r16800cc i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary burst interruption [read interrupted by read] burst read operation can be interrupted by new read of any bank. random column access is allowed. read to read interval is minimum 1clk. read interrupted by read (bl=8, cl=2) command a0-9,11 a10 ba0,1 dq yi read read read read yj yk yl 0 0 0 0 00 10 00 01 dqs qai0 qai1 qaj0 qaj1 qaj2 qaj3 qak0 qak1 qak2 qak3 qak4 qak5 qal0 qal1 qal2 qal3 qal4 qal5 qal6 qal7 /clk clk [read interrupted by precharge] burst read operation can be interrupted by precharge of the same bank. read to pre interval is minimum 1 clk. a pre command to output disable latency is equivalent to the /cas latency. as a result, read to pre interval determines valid data length to be output. the figure below shows examples of bl=8. read interrupted by precharge (bl=8) cl=2.0 /clk clk command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs
28 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc i i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary read interrupted by precharge (bl=8) cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 /clk clk dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs read interrupted by precharge (bl=8) cl=3.0 /clk clk command dqs command dq command dq dq pre read read pre q0 q1 q2 q3 q4 q5 read pre dqs q0 q1 q2 q3 dqs q0 q1
integrated silicon solution, inc. 29 rev. a 06/01/09 is43r16800cc zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary burst read operation can be interrupted by a burst stop command(term). read to term interval is minimum 1 clk. a term command to output disable latency is equivalent to the /cas latency. as a result, read to term interval determines valid data length to be output. the figure below shows examples of bl=8. [read interrupted by burst stop] read interrupted by term (bl=8) /clk clk cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs cl=2.0 command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs
30 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc [read interrupted by write with term] read interrupted by term (bl=8) /clk clk cl=2.5 command dq q0 q1 q2 q3 read term dqs write d0 d1 d2 d3 d4 d5 cl=2.0 command dq q0 q1 q2 q3 read term dqs write d0 d1 d2 d3 d4 d5 d6 d7 read interrupted by term (bl=8) /clk clk cl=3.0 command dqs command dq command dq dq term read read term q0 q1 q2 q3 q4 q5 read term dqs q0 q1 q2 q3 dqs q0 q1 cl=3.0 command dq q0 q1 q2 q3 read term dqs write d0 d1 d2 d3 d4 d5
integrated silicon solution, inc. 31 rev. a 06/01/09 is43r16800cc burst write operation can be interrupted by write of any bank. random column access is allowed. write to write interval is minimum 1 clk. [write interrupted by write] [write interrupted by read] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. internal write to read command interval(twtr) is minimum 1 clk. the input data on dq at the interrupting read cycle is "don't care". twtr is referenced from the first positive edge after the last data input. write interrupted by read (bl=8, cl=2.5) command a0-9,11 a10 ba0,1 dq write yi 0 00 read yj 0 00 dai0 dai1 qaj0 qaj1 qaj2 qaj3 qs qaj4 qaj5 qaj6 qaj7 dm twtr /clk clk write interrupted by write (bl=8) command a0-9,11 a10 ba0,1 write yi 0 00 write yk 0 10 write yj 0 00 write yl 0 00 dq dai1 daj1 daj3 dak1 dak3 dak5 dal1 dqs dal2 dal3 dal5 dal6 dal7 dal4 dal0 dak4 dak2 dak0 dai0 daj0 daj2 /clk clk
32 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc i i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary burst write operation can be interrupted by precharge of the same or all bank. random column access is allowed. twr is referenced from the first positive clk edge after the last data input. [write interrupted by precharge] write interrupted by precharge (bl=8, cl=2.5) command a0-9,11 a10 ba0,1 dq write yi 0 00 pre 00 dai0 dai1 qs dm twr /clk clk
integrated silicon solution, inc. 33 rev. a 06/01/09 is43r16800cc i zentel electronics corporation ddr sdram (rev.1.1) a3s56d30/40etp 256m double data rate synchronous dram preliminary preliminary [initialize and mode register sets] command /clk clk emrs pre nop mrs pre ar ar mrs act code code xa code xa 1 0 xa a0-1 1 a10 code 1 ba0,1 dqs dq 1 0 0 0 0 code tmrd tmrd trp trfc trfc tmrd mode register set, reset dll extended mode register set [auto refresh] single cycle of auto-refresh is initiated with a refa(/cs=/ras=/cas=l,/we=cke=h) command. the refresh address is generated internally. 4096 refa cycles within 64ms refresh 128 mbits memory cells. the auto-refresh is performed on 4 banks concurrently. before performing an auto refresh, all banks must be in the idle state. auto-refresh to auto-refresh interval is minimum trfc . any command must not be supplied to the device before trfc from the refa command. auto-refresh /ras cke /cs /cas /we a0-12 ba0,1 nop or deselect trfc auto refresh on all banks auto refresh on all banks /clk clk cke initialize and mrs
34 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc [self refresh] self -refresh mode is entered by issuing a refs command (/cs=/ras=/cas=l,/we=h,cke=l). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self- refresh mode, cke is asynchronous and the only enable input, all other inputs including clk are disabled and ignored, so that power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke for longer than txsnr/txsrd. self-refresh /ras cke /cs /cas /we a0-1 1 ba0,1 txsnr self refresh exit /clk clk x y x y txsrd
integrated silicon solution, inc. 35 rev. a 06/01/09 is43r16800cc the purpose of clk suspend is power down. cke is synchronous input except during the self- refresh mode. a command at cycle is ignored. from cke=h to normal function, dll recovery time is not required in the condition of the stable clk operation during the power down mode. [power down] /clk clk power down by cke command pre cke command act cke standby power down nop nop valid nop nop valid active power down dm is defined as the data mask for writes. during writes,dm masks input data word by word. dm to write mask latency is 0. [dm control] dm function(bl=8,cl=2) command dqs dq dm write read d0 d1 d3 d4 d5 d6 d7 masked by dm=h don't care q2 q3 q4 q5 /clk clk q0 q1 q6 txpnr/txprd
36 integrated silicon solution, inc. rev. a 06/01/09 is43r16800cc ordering information - v d d = 2.5v commercial range: 0c to +70c frequency speed (ns) order part no. package 200 mhz 5 is43r16800cc-5tl 66-pin tsop-ii, lead-free 166 mhz 6 IS43R16800CC-6TL 66-pin tsop-ii, lead-free industrial range: -40c to +85c frequency speed (ns) order part no. package 200 mhz 5 is43r16800cc-5tli 66-pin tsop-ii, lead-free 166 mhz 6 IS43R16800CC-6TLi 66-pin tsop-ii, lead-free
integrated silicon solution, inc. 37 rev. a 06/01/09 is43r16800cc note : 4. formed leads shall be planar with respect to one another within 0.1mm 3. dimension b does not include dambar protrusion/intrusion. 2. dimension d and e1 do not include mold protrusion . at the seating plane after final test. 1. controlling dimension : mm package outline 10/04/2006

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